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2.7 V to 5.5 V, <100 A, 8-/10-/12-Bit nanoDACTM D/A, SPI(R) Interface, SC70 Package
Preliminary Technical Data
FEATURES
6-lead SC70 package Power-down to <100 nA @ 3 V Micropower operation: max 100 A @ 5 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility Minimized zero code error AD5601 buffered 8-bit DAC in SC70: B Version: 0.5 LSB INL AD5611 buffered 10-bit DAC in SC70: A Version: 4 LSB INL AD5621 buffered 12-bit DAC in SC70: A Version: 6 LSB INL
AD5601/AD5611/AD5621
FUNCTIONAL BLOCK DIAGRAM
VDD GND POWER-ON RESET
AD5601/AD5611/AD5621
DAC REGISTER
REF(+) 14-BIT DAC OUTPUT BUFFER VOUT
INPUT CONTROL LOGIC
POWER-DOWN CONTROL LOGIC
RESISTOR NETWORK
04783-4-001
SYNC
SCLK
DIN
Figure 1.
Table 1. Related Devices
APPLICATIONS
Voltage level setting Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
Part Number AD5641
Description 2.7 V to 5.5 V, <100 A, 14-Bit, nanoDAC D/A, tiny SC70 Package
GENERAL DESCRIPTION
The AD5601/AD5611/AD5621, members of the nanoDAC family, are single, 8-/10-/12-bit, buffered, voltage out DACs that operate from a single 2.7 V to 5.5 V supply, consuming <100 A at 5 V. The parts come in a tiny SC70 package. Their on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5601/AD5611/AD5621 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. The reference for the AD5601/AD5611/AD5621 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. The parts incorporate a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write to the device takes place. The AD5601/AD5611/AD5621 contain a power-down feature that reduces current consumption to <100 nA at 3 V, and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. The low power consumption of these parts in normal operation makes them ideally suited to portable batteryoperated equipment. The combination of small package and low power makes these nanoDAC devices ideal for level-setting requirements such as generating bias or control voltages in space-constrained and power-sensitive applications. (continued on Page 3)
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5601/AD5611/AD5621 TABLE OF CONTENTS
Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function DescriptionS ............................ 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 General Description ....................................................................... 13 D/A Section................................................................................. 13 Resistor String............................................................................. 13 Output Amplifier........................................................................ 13 Serial Interface ............................................................................ 13
Preliminary Technical Data
Input Shift Register .................................................................... 13 SYNC Interrupt .......................................................................... 14 Power-On Reset.......................................................................... 14 Power-Down Modes .................................................................. 14 Microprocessor Interfacing....................................................... 14 Applications..................................................................................... 16 Choosing a Reference as Power Supply for AD5601/AD5611/AD5621 ....................................................... 16 Bipolar Operation Using the AD5601/ AD5611/AD5621.... 16 Using AD5601/AD5611/AD5621 with an Opto-Isolated Interface ....................................................................................... 17 Power Supply Bypassing and Grounding................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
Revision PrD: Preliminary Version
Rev. PrD | Page 2 of 20
Preliminary Technical Data PRODUCT HIGHLIGHTS
1. 2. Available in a space-saving 6-lead SC70 package. Low power, single-supply operation. The AD5601/ AD5611/AD5621 operate from a single 2.7 V to 5.5 V supply and typically consume 0.2 mW at 3 V and 0.5 mW at 5 V, making them ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/s. 4. 5. 6. 7.
AD5601/AD5611/AD5621
Reference derived from the power supply. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. Power-down capability. When powered down, the DAC typically consumes <100 nA at 3 V.
3.
Rev. PrD | Page 3 of 20
AD5601/AD5611/AD5621 SPECIFICATIONS
Preliminary Technical Data
VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
A Grade1, 2 Parameter STATIC PERFORMANCE AD5601 Resolution Relative Accuracy 3 (INL) Differential Nonlinearity (DNL) AD5611 Resolution Relative Accuracy 3 (INL) Differential Nonlinearity (DNL) AD5621 Resolution Relative Accuracy 3 (INL) Differential Nonlinearity (DNL) Zero code Error Full-Scale Error Offset Error Gain Error Zero code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS4 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive load stability Output noise spectral density noise Digital-to-Analog Glitch Impulse Digital Feedthrough Short Circuit Current DC Output Impedance LOGIC INPUTS Input Current VINH, Input High Voltage VINL, Input Low Voltage Pin input Capacitance POWER REQUIREMENTS * * * * * * * * * * * * * * * * * 0. 8 0. 6 3
Min Typ2 Max Min
B Grade2
Typ2 Max
Unit
Test Conditions/Comments
8 0. 5 1 10 4 1 12 6 1 * * * * * * * * 0 6 0. 5 470 1000 120 2 5 0.2 20 1 1 1. 8 1. 4 0. 2 0. 01 10 0. 037 5. 0 2. 0 VDD 10
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV LSB mV %FSR V/c ppm FSR/C V s V/s pf pf nV/hz uv nV-s nV-s mA A V V V V pF Guaranteed monotonic by design All 0's loaded to DAC register All 1's loaded to DAC register Guaranteed monotonic by design Guaranteed monotonic by design
Code 1/4 to 3/4 RL = RL = 2k Dac code = midscale,1 khz Dac code = midscale, 0.1hz to 10 khz bandwidth 1LSB change around major carry Vdd =3v/5v
Vdd = 5. 0V Vdd = 2. 7V Vdd = 5. 0V Vdd = 2 .7V
Rev. PrD | Page 4 of 20
Preliminary Technical Data
A Grade1, 2 Parameter Vdd ( normal mode ) VDD = 4.5 v to 5.5 v VDD = 2.7 v to 3.6 v IDD ( All power down modes) VDD = 4.5 v to 5.5 v VDD = 2.7 v to 3.6 v POWER EFFICIENCY Iout/Idd
1
AD5601/AD5611/AD5621
B Grade2
Max Min Typ2 Max Typ2
Min
Unit V
Test Conditions/Comments All digital inputs at 0 or VDD VIH = VDD and VIL = GND VIH = VDD and VIL = GND
*
* * *
2.7
5. 5 100 70
* * tbd
* *
0.2 0. 05 tbd
1 1
%
VIH = VDD and VIL = GND VIH = VDD and VIL = GND Iload = 2ma and VDD = 5V
Asterisk (*) = specifications same as B grade. 2 Temperature ranges are as follows: B Version: -40C to +125C, typical at +25C. 3 Linearity calculated using a reduced code range.
4
Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 3.
Parameter t12 t2 t3 t4 t5 t6 t7 t8 t9 Limit1 33 13 12 13 5 4.5 0 33 13 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore
1 2
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 30 MHz.
t4
SCLK
t2
t1
t9
t8
SYNC
t3 t6 t5
t7
DIN
D15
D14
D2
D1
D0
D15
D14
Figure 2. Timing Diagram
Rev. PrD | Page 5 of 20
04783-C-002
AD5601/AD5611/AD5621 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature SC70 Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) ESD Rating -0.3 V to +7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +160C 150C 332C/W 120C/W 215C 220C 2.0 kV
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD | Page 6 of 20
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC 1 SCLK 2 DIN 3 TOP VIEW 4 VDD (Not to Scale)
04783-C-003
AD5601/AD5611/AD5621
AD5601/ AD5611/ AD5621
6 VOUT 5 GND
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 Mnemonic SYNC Function Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. Ground Reference Point for All Circuitry on the AD5601/AD5611/AD5621. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
2 3 4 5 6
SCLK DIN VDD GND VOUT
Rev. PrD | Page 7 of 20
AD5601/AD5611/AD5621 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in Figure 4. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL versus code plot can be seen in Figure 7. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5601/AD5611/AD5621, because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of zero-code error versus temperature can be seen in Figure 6. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error versus temperature can be seen in Figure 6. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range.
Preliminary Technical Data
Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account. A typical TUE versus code plot can be seen in Figure 5. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 17. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
Rev. PrD | Page 8 of 20
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
2.5 2.0 1.5 0.5 0.4 0.3
AD5601/AD5611/AD5621
DNL ERROR (LSBs)
04783-C-004
INL ERROR (LSBs)
1.0 0.5 0 -0.5 -1.0 -1.5 0 2k 4k 6k 8k CODE 10k 12k 14k 16k
0.2 0.1 0 -0.1 -0.2 -0.3 0 2k 4k 6k 8k CODE 10k 12k 14k 16k
04783-C-007
Figure 4. Typical INL Plot
Figure 7. Typical DNL Plot
18 16 14 12
TUE (LSBs)
10 8 6 4 2 0 256 2k 4k 6k 8k CODE 10k 12k 14k 16k
04783-C-005
Figure 5. Total Unadjusted Error
Figure 8. INL and DNL vs. Supply
Figure 6. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 9. IDD Histogram @ VDD = 3 V/5 V
Rev. PrD | Page 9 of 20
AD5601/AD5611/AD5621
0.8 VDD = 5V TA = 25C DAC LOADED WITH FF CODE 0.4
Preliminary Technical Data
0.6
VO (V)
0.2
0.0
-0.2 DAC LOADED WITH 00 CODE -0.4
04783-C-010
-0.6 -15 -10 -5 0 I (mA) 5 10 15
Figure 10. Source and Sink Current Capability
Figure 13. Supply Current vs. Code
Figure 11. Supply Current vs. Temperature
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Full-Scale Settling Time
Figure 15. Half-Scale Settling Time
Rev. PrD | Page 10 of 20
Preliminary Technical Data
VDD = 5V TA = 25C VDD
AD5601/AD5611/AD5621
VDD = 5V TA = 25C MIDSCALE LOADED
CH1
CH1
VOUT = 70mV
04783-C-016
CH2 CH1 1V, CH2, TIME BASE = 20s/DIV
CH1 5uV/DIV
Figure 16. Power-On Reset to 0 V
CH1 VDD VDD = 5V TA = 25C
Figure 19. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
VDD = 5V TA = 25C
CH1
CLK
CH2
CH2 VOUT
04783-C-017
VOUT
04783-C-020
CH1 1V, CH2 5V, TIME BASE = 50s/DIV
CH1 5V, CH2 1V, TIME BASE = 5s/DIV
Figure 17. VDD vs. VOUT (Power-Down)
Figure 20. Exiting Power-Down
Figure 18. Digital-to-Analog Glitch Impulse
Figure 21. Harmonic Distortion on Digitally Generated Waveform
Rev. PrD | Page 11 of 20
04611-A-019
AD5601/AD5611/AD5621
140 FULL SCALE 120 3/4 SCALE 100 1/4 SCALE 80 160 MIDSCALE 140 120 MIDSCALE 200 180
Preliminary Technical Data
NOISE SPECTRAL DENSITY CODE 0x2040
nV/ Hz
IDD (uA)
100 80 60
FULL SCALE
60 40 20
ZERO SCALE
ZERO SCALE 40 20 10K FREQUENCY 100K
04783-C-024
0
5
10
15
20
25
FREQUENCY (MHz)
04783-C-023
0
0 1K
Figure 22.IDD vs. SCLK vs. Code
Figure 23. Noise Spectral Density
Rev. PrD | Page 12 of 20
Preliminary Technical Data GENERAL DESCRIPTION
D/A SECTION
The AD5601/AD5611/AD5621 DAC are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 24 is a block diagram of the DAC architecture.
VDD
AD5601/AD5611/AD5621
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen inFigure 10. The slew rate is 0.5 V/s, with a halfscale settling time of 8 s with the output unloaded.
REF (+) DAC REGISTER RESISTOR NETWORK REF (-) OUTPUT AMPLIFIER VOUT
SERIAL INTERFACE
The AD5601/AD5611/AD5621 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5601/AD5611/AD5621compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line might be kept low or brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 1.8 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part, as mentioned above. However, it must be brought high again just before the next write sequence.
04783-C-025
GND
Figure 24. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal output voltage is given by
D VOUT = V DD x N 2 where D is the decimal equivalent of the binary code that is loaded to the DAC register.
RESISTOR STRING
The resistor string section is shown in Figure 25. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
INPUT SHIFT REGISTER
R
R
R
TO OUTPUT AMPLIFIER
The input shift register is 16 bits wide (see Figure 26). The first two bits are control bits that control which mode of operation the power is in (normal mode or any one of three power-down modes). For a complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits, which are transferred to the DAC register on the 16th falling edge of SCLK.
DB15 (MSB) DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
DATA BITS
04783-C-026
R
1 1
0 1
100 k TO GND THREE-STATE
POWER-DOWN MODES
Figure 25. Resistor String Section
Figure 26. Input Register Contents
Rev. PrD | Page 13 of 20
04783-C-027
0 0
0 1
NORMAL OPERATION 1 k TO GND
AD5601/AD5611/AD5621
SCLK
Preliminary Technical Data
SYNC
04783-C-028
DIN
DB15
DB0
DB16
DB0
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH FALLING EDGE
Figure 27. SYNC Interrupt Facility
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 27).
the part is in power-down mode. There are three different options: the output is connected internally to GND through a 1 k resistor or a 100 k resistor, or the output is left opencircuited (three-state). Figure 28 shows the output stage.
RESISTOR STRING DAC
AMPLIFIER
VOUT
POWER-ON RESET
The AD5601/AD5611/AD5621 contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications in which it is important to know the state of the DAC's output while it is in the process of powering up.
Figure 28. Output Stage During Power-Down
POWER-DOWN MODES
The AD5601/AD5611/AD5621 have four separate modes of operation. These modes are software-programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows how the state of the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation for the AD5601/AD5611/ AD5621
DB15 0 0 1 1 DB14 0 1 0 1 Operating Mode Normal operation Power-down mode 1 k to GND 100 k to GND Three-state
The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when the powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s for VDD = 3 V. See Figure 20 for a plot.
MICROPROCESSOR INTERFACING
AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface
Figure 29 shows a serial interface between the AD5601/ AD5611/AD5621 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
ADSP-2101/ ADSP-2103*
TFS DT SCLK
When both bits are set to 0, the part works normally with its normal power consumption of 100 A maximum at 5 V. However, for the three power-down modes, the supply current falls to <100 nA at 3 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while
AD5601/AD5611/ AD5621*
SYNC
04783-C-030
DIN SCLK
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 29. AD5601/AD5611/AD5621 to ADSP-2101/ADSP-2103 Interface
Rev. PrD | Page 14 of 20
04783-C-029
POWER-DOWN CIRCUITRY
RESISTOR NETWORK
Preliminary Technical Data
AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
Figure 30 shows a serial interface between the AD5601/ AD5611/AD5621 and the 68HC11/68L11 microcontrollers. SCK of the 68HC11/68L11 drives the SCLK of the AD5601/ AD5611/AD5621, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5601/AD5611/AD5621, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.
68HC11/ 68L11
PC7 SCK MOSI
AD5601/AD5611/AD5621
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 32 shows a serial interface between the AD5601/ AD5611/AD5621 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5601/AD5611/AD5621, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 transmit data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 output the serial data in a format that has the LSB first. The AD5601/AD5611/AD5621 require their data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
AD5601/AD5611/ AD5621*
SYNC
04783-C-031
AD5601/AD5611/ AD5621*
SYNC
04783-C-033 04783-C-034
P3.3 TXD RXD
SCLK DIN
SCLK DIN
*ADDITIONAL PINS OMITTED FOR CLAIRTY
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 32. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 30. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
AD5601/AD5611/AD5621 to MICROWIRE Interface AD5601/AD5611/AD5621 to Blackfin(R) ADSP-BF53X Interface
Figure 31 shows a serial interface between the AD5601/ AD5611/AD5621 and the Blackfin ADSP-BF53x microprocessors. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/ AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/AD5621, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0.
ADSP-BF53X
Figure 33 shows an interface between the AD5601/AD5611/ AD5621 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5601/AD5611/AD5621 on the rising edge of the SK.
MICROWIRE*
AD5601/AD5611/ AD5621*
SYNC SCLK DIN
CS SK SO
AD5601/AD5611/ AD5621
DIN
04783-C-032
*ADDITIONAL PINS OMITTED FOR CLAIRTY
DT0PRI TSCLK0 TFS0
Figure 33. AD5601/AD5611/AD5621 to MICROWIRE Interface
SCLK SYNC
*ADDITIONAL PINS OMITTED FOR CLAIRTY
Figure 31. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53X Interface
Rev. PrD | Page 15 of 20
AD5601/AD5611/AD5621 APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY FOR AD5601/AD5611/AD5621
The AD5601/AD5611/AD5621 come in a tiny SC70 package with less than 100 A supply current. Because of this, the choice of reference depends on the application requirement. For spacesaving applications, the ADR425 is available in an SC70 package and has excellent drift at 3 ppm/C. It also provides very good noise performance at 3.4 V p-p in the 0.1 Hz to 10 Hz range. Because the supply current required by the AD5601/AD5611/ AD5621 is extremely low, the parts are ideal for low supply applications. The ADR293 voltage reference is recommended in this case. This requires 15 A of quiescent current and can, therefore, drive multiple DACs in one system, if required.
7V 5V
Preliminary Technical Data
BIPOLAR OPERATION USING THE AD5601/ AD5611/AD5621
The AD5601/AD5611/AD5621 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 35. The circuit in Figure 35 gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
D R1 + R2 R2 VO = VDD x N x - VDD x R1 2 R1
where D represents the input code in decimal (0-2N).
ADR425
With VDD = 5 V, R1 = R2 = 10 k:
10 x D VO = N - 5V 2 This is an output voltage range of 5 V with 0x0000 corresponding to a -5 V output, and 0x3FFF corresponding to a +5 V output.
R2 = 10k +5V +5V R1 = 10k AD820/ OP295 VDD 10F 0.1F VOUT -5V 5V
DIN
Figure 34. ADR425 as Power Supply to the AD5601/AD5611/AD5621
Some recommended precision references for use as supplies to the AD5601/AD5611/AD5621 are listed in Table 7.
Table 7. Precision References for Use with AD5601/AD5611/ AD5621
Part No. ADR435 ADR425 ADR02 ADR395 Initial Accuracy (mV max) 6 6 5 6 Temperature Drift (ppm/C max) 3 3 3 25 0.1 Hz to 10 Hz Noise (V p-p typ) 3.4 3.4 15 5
04783-C-035
3-WIRE SERIAL INTERFACE
SYNC SCLK
AD5601/AD5611/ AD5621
VOUT = 0V TO 5V
AD5601/AD5611/ AD5621
3-WIRE SERIAL INTERFACE
Figure 35. Bipolar Operation with the AD5601/AD5611/AD5621
Rev. PrD | Page 16 of 20
04783-C-036
Preliminary Technical Data
USING AD5601/AD5611/AD5621 WITH AN OPTOISOLATED INTERFACE
In process-control applications in industrial environments, it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial logic interface, they require only three opto-isolators to provide the required isolation (see Figure 36). The power supply to the parts also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5601/AD5611/AD5621.
+5V REGULATOR POWER 10F 0.1F
AD5601/AD5611/AD5621
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5601/ AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/ AD5611/AD5621 are in a system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close to the AD5601/AD5611/AD5621 as possible. The power supply to the AD5601/AD5611/AD5621 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor have low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
VDD 10k SCLK SCLK VDD
VDD 10k SYNC SYNC
AD5601/ AD5611/ AD5621
VOUT
VDD 10k DATA DIN GND
04783-C-037
Figure 36. AD5601/AD5611/AD5621 with an Opto-Isolated Interface
Rev. PrD | Page 17 of 20
AD5601/AD5611/AD5621 OUTLINE DIMENSIONS
2.00 BSC
6 5 2 4
Preliminary Technical Data
1.25 BSC
1 3
2.10 BSC
PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB SEATING PLANE 8 4 0
0.10 MAX
0.46 0.36 0.26
Figure 37. 6-Lead Plastic Surface Mount Package [SC70] (KS-6) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5611AKS AD5621AKS Temperature Range -40C to +125C -40C to +125C Description 4.0 LSB INL 6.0 LSB INL Package Description 6-Lead Plastic Surface Mount Package (SC70) 6-Lead Plastic Surface Mount Package (SC70) Package Option KS-6 KS-6
Rev. PrD | Page 18 of 20
Preliminary Technical Data NOTES
AD5601/AD5611/AD5621
Rev. PrD | Page 19 of 20
AD5601/AD5611/AD5621 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR04783-0-11/04(PrD)
Rev. PrD | Page 20 of 20

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